GSoC 2018 Final Report
Project Overview: Bit Error Ratio testers are used to test the quality of signal transreception on a given medium. They also assist in tuning transmitter and receiver parameters so that medium fidelity is maximized. Several secure IP cores exist which may be implemented on FPGA to serve this purpose, one example being iBERT LogiCore by Xilinx. iBERT LogiCore is a GUI application which provides a nice interface for the user to change parameters such as prbs config, output swing, pre/post cursor settings, equalizer settings, etc. and observe the changes in bit error ratio. My project, as part of Google Summer of Code 2018, was to design and test an opensource equivalent of iBERT LogiCore and add most features as detailed in its datasheet. All files are coded in python-based HDL framework - migen and use an SOC ecosystem based on Migen - LiteX , to create the necessary host connections. This IP majorly uses 7 series MGT transceiver primitives GTPE2_COMMON and GTPE2_CHANNEL. Code