GSoC 2018 Blog
Bit Error Ratio Analyzer using Litex

I have completed coding a basic version of Bit Error Ratio Analyser. Features: 1) MGT Settings: 2) BER Settings: 3) DRP Interface Code :  1) All coded files may be found here: https://github.com/harshgugale/ber_analyzer_gtp  2) Litex local install is necessary. Next Steps: 1) Thorough testing of these modules is left. I will begin thorough testing from Monday when Florent will be back to his office. 2) I will also try to complete documenting my code until then. My next post will contain the final report for this GSoC project. It will contain information to reproduce results, list coded features and possible improvements. 3) I had planned to also plot a statistical eye, but I feel that due to time constraints this wont be possible. I will work on this after GSoC.

1) Completed integrating functionality to read/write from the host through DRP. 2) BER Analyzer now supports TX/RX reset from host, PLL lock status intimation, changing loopback mode (Near End PMA or Normal), changing TX/RX polarity inversion. 3) Read about eye scan architecture. Next Steps: 1) Using DRP write, include functionality to change pre emph, post emph and output swing in the next two days. 2) Update GUI with handlers to support these functions 3) I will start coding and plotting the eye scan from next week.

1) Completed integrating TX/RX host reset functionality. 2) Also integrated PLL Status intimation to user. 3) Coded DRP read/write interface to work with the host commands and the RX init commands. Next Steps : 1) Test DRP read/write on the FPGA. 2) Start by adding feature: 1) Loopback mode 2) TX/RX Polarity

1) Completed integration of clock Aligner class and testing of Near end PMA loopback on te014 board. 2) All PRBS features tested on Arty board now work on te014 board over MGTs. GUI has not been updated with event handlers specific to MGT settings. Code: 1) Coded files may be found here : https://github.com/harshgugale/ber_analyzer_gtp Next Steps: 1) I have started with the addition of TX/RX reset from the host. I will complete the same in the next two days. 2) I can then integrate DRP read/write class with the main class and add precursor, post-cursor and output swing control.

1) Implemented simple PMA loopback on te014 board with PRBS data. This was achieved without alignment. 2) There seems to be some issue with the BruteForceClockAligner class and hence the receiver never completes reseting to output the correct phase. 3) Updated the GUI to include MGT functions. Next steps: 1) Look into the issue with the clock aligner class. 2) Add MGT setting event handlers.

1) Integrated GTP Primitives, clock aligner file, top class to connect GTP COMMON and CHANNEL with base SOC file prepared using LiteX libraries 2) Coded DRP FSM class to read/write through DRP interface. 3) Updated GUI to inform the user regarding - PLL lock status, MGT Link, TX/RX Polarity, TX/RX reset. Next Steps: 1) Due to some connectivity issues, I could not implement my design on the FPGA. I will resolve the same and implement in the next 3 days.

1) Integrated clock aligner module with Simulation file. 2) Updated PRBS module to work with data_width = 20. 3) Updated prbs_control file to first align bits received from the RX interface. 4) Received FPGA sent by Florent. Next Steps : 1) Implement design on FPGA. 2) Add functionality to read/ write primitive attributes using DRP interface. We have discussed a rough plan for the coming month Till 15th July - Integrate Clock aligner Module, implement on FPGA and debug if any issues. If time permits code functions to read/write primitive attributes using DRP interface 15th  July - 23rd July - Add features: 1) RX/TX reset, channel reset 2) PLL Lock status 3) Link 4) Loopback mode 5) TX/RX Polarity 23rd July - 31st July -  1) TX Output Swing 2) Precursor control 3) Post cursor control 1st Aug - 6th Aug - Explore Eye scan architecture and if time permits, plot the same. 7th Aug - 12th Aug - Documentation, merging of code and submissions

Updates till now : 1) Simulation and testing (on Arty Board) of the PRBS trans reception module are complete. All features concerning BERT settings for a single MGT available in IBERT logiCore have been integrated. Additionally, user selectable 8b10b encoding module has been incorporated. 2) GUI to control PRBS config, inject user selectable error, display Bit Error Ratio, and Link availability has been designed and tested on Arty Board. 3) Completed the simulation of a simple near-end PMA loopback of Multi-Gigabit serial trans-reception module. Also, integrated PRBS modules prepared earlier with this file. 4) Unfortunately, the FPGA sent by my mentor, Florent is stuck at the customs office in India. I will order a new board for myself, but it may take some time to arrive. Code : 1) All python files may be found here: https://github.com/harshgugale. ber_analyser_gtp has files to simulate a loopback test using Xilinx Vivado. ber_analyser_arty contains GUI files and asso

1) TX and RX init sequences are now working, and I have a good understanding of transceiver operations and terminologies. 2) An excellent material related to MGTs, their operation modes, reasons behind required logic and applications is https://arrc.ou.edu/~rockee/RIO/serialio-book.pdf. 3) I also had my Visa interview on the 2nd of July so could not work on the 1st and 2nd. Next steps: 1) Simulate a simple near-end PMA loopback test using PRBS modules prepared by me.