GSoC 2018 Blog
Bit Error Ratio Analyzer using Litex

1) PRBS generator and checker modules have been prepared. They can be viewed here: https://github.com/harshgugale/ber_analyzer_arty . Next Steps: 1) Add support to control config and intimate status to host through LiteX libraries. 2) Add Module to introduce controlled errors in the PRBS Transmitter. 3) Implement design on Arty board.

1) Analysed working of some more Migen modules such as migen.fhdl.structure.py and migen.genlib.cdc.py to become familiar with how Migen handles datatypes. 2) Since clock domain crossing will be a significant part of the project, I analyzed how Migen takes care of synchronizations and avoids metastability. Saw the working of Multireg, Clockdomainrenamer functions. 3) Understood how PRBS module (https://github.com/enjoy-digital/transceiver_test/blob/master/transceiver/prbs.py) is coded and how to use it. 4) Read some literature about 8b/10b encoding. Understood the code here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/code_8b10b.py 5) Started coding the Tx_top module (architecture and placement of the same can be found in the previous post). Can't seem to figure out the generation of invalid data for the first 2 clock cycles from this modules. We have decided to go forward with this since the PRBS checker module should be able to synchronize the same

1) I now have a complete block level understanding of the GTP transceivers. This is the user guide referred: https://www.xilinx.com/support/documentation/user_guides/ug482_7Series_GTP_Transceivers.pdf Next Steps : 1) As discussed with Florent, I will first implement the complete system on my Arty Board which will validate the datapath. 2) Roughly, following modules will be coded, integrated and verified on FPGA. 3) The left half of the system will be created using LiteX libraries. 4) Work for the next three days would be to code and integrate the modules and if time permits implement the design and perform a loopback test.

1) Took a deeper look into LiteX workflow and understood use of Litex_server file, CSR related files, target files etc. Tried some other very trivial programs to get a grasp of working with LiteX. 2) Tried to understand GTP transceiver files coded by my Mentor, and started reading the 7- Series Transceiver User Guide. Next steps: 1) Since the User Guide is a pretty long document it may take quite some time to read and correlate with our use case. Work for the next three days would be to read the entire document once and try to get a very rough idea how GTP transceiver files were coded.

Almost forgot about the blog :p. The official coding period began on the 14th of May, and work completed by me till now is as follows : 1) Migen : I now have a satisfactory understanding of working with Migen. Personally, I feel Migen framework is more intuitive and provides a nice abstraction layer so that we can focus more on the logic part rather than usual humdrums ommon in Verilog such as initializations, datatype conflict, driver conflicts, etc Anyone looking to learn Migen can go through these links : - https://m-labs.hk/migen/manual/ - http://blog.lambdaconcept.com/doku.php - https://github.com/m-labs/migen/tree/master/examples These pretty much cover everything. 2) Installed Vivado and cable drivers: I switched entirely to Ubuntu about 3 months back, so I needed to again install Vivado and the cable drivers for my FPGA - Arty board from Digilent. Cable drivers require sudo privileges so are not installed by default. 3) LiteX: I started learning about LiteX