GSoC 2018 Final Report

Project Overview:

Bit Error Ratio testers are used to test the quality of signal transreception on a given medium. They also assist in tuning transmitter and receiver parameters so that medium fidelity is maximized.

Several secure IP cores exist which may be implemented on FPGA to serve this purpose, one example being iBERT LogiCore by Xilinx. iBERT LogiCore is a GUI application which provides a nice interface for the user to change parameters such as prbs config, output swing, pre/post cursor settings, equalizer settings, etc. and observe the changes in bit error ratio.

My project, as part of Google Summer of Code 2018, was to design and test an opensource equivalent of iBERT LogiCore and add most features as detailed in its datasheet. All files are coded in python-based HDL framework - migen and use an SOC ecosystem based on Migen - LiteX, to create the necessary host connections. This IP majorly uses 7 series MGT transceiver primitives GTPE2_COMMON and GTPE2_CHANNEL.

Coded files may be found here.

A block diagram of the IP is shown below:

Implementation guide: 

I have tested this design on TE7014 FPGA board which has Artix-7 FPGA and GTP transceivers.

1) Make sure you have an updated Vivado toolchain installed on your computer. I have synthesized and tested this design using Vivado v2018.1. Since the design uses many default attribute values in primitives, older versions may have some inconsistent values.

2) Install python3.

2) Install Migen - https://m-labs.hk/migen/manual/introduction.html#installing-migen

3) Clone repo - https://github.com/enjoy-digital/ber_analyzer_gsoc2018_harsh_gugale
($ git clone https://github.com/enjoy-digital/ber_analyzer_gsoc2018_harsh_gugale)

4) Run file litex_local_install.py to clone LiteX libraries.
($ python3 litex_local_install.py)

5) Run file te014.py. ($ python3 te014.py)

6) Connect FPGA and load gateware (Follow build examples here)

7) Run litex_server.py. (eg command : $ python3 litex_server.py uart /dev/ttyUSB0)

8) Open another terminal and navigate to the project parent directory

9) Run file ./gui/ber_gui.py ($ python3 ./gui/ber_gui.py)

Current status:

1) PRBS Generator and checker :

• LFSR based PRBS generator and checker modules. (PRBS 7,15,23,31 settings available).
• User selectable 8b10b encoding integrated.
• Bit error ratio intimation to the user and variable error injection complete.
• Clock Aligner module was integrated at RX.

2) GUI :

• MGT Settings : 
• MGT link status label: label sets to LINK when RX receives 100 bits without any error
• MGT linerate label: Serial transreception rate.
• PLL Status label:  Lock status of GTPE2_COMMON PLL. Label sets to LOCKED if pll locked.
• TX/RX Reset button: Resets the TX/RX interface.
• TX/RX polarity invert checkbox: Inverts the polarity of gtptx and gtprx serial output/input ports.
• Disable Near end PMA loopback checkbox.
•  TX precursor/ post cursor combobox: User selectable pre/post cursor ISI reduction.
• TX Output Swing combo box: Manipulates the TX Output differential voltage.

• BER Settings 
• TX/RX PRBS config combobox : User selectable PRBS 7, 15, 23, 31 config.
• Error inject combo box : Capable of injecting 0%, 25%, 50%, 75% and 100% errors.
• Real-time BER intimation label. BER gets updated every 1 second.

• DRP Interface :
• Dynamic Reconfiguration port interface for real-time modification of primitive attributes. 

Possible improvements:

1) Creating multiple instances of MGT: Currently, Bit error ratio analyzer supports only one MGT instance. More than one may be added which may be selectable by the user while core generation.

2) Plot statistical eye: Statistical eye can give an excellent estimate of the line fidelity. 7 series GTP transceivers primitives support this functionality and one can plot it using python libraries such as matplotlib. This functionality was planned to have been completed in GSoC, but I couldn't finish it due to time constraints.

3) Currently, linerates less than 3.5Gbps work (clock Alignment fails on linerates greater than this). Better clock routing may be explored.


Acknowledgment:

My sincere thanks and appreciation to my mentor, Florent Kermarrec who has been relentlessly advising me on better design strategies, providing me with relevant resources as and when I need them, and answering my silliest of doubts with patience. Thank you, Florent!

Also, a big thank you to TimVideos for selecting me. I will be working on this after GSoC as well, to improve upon the project's shortcomings.

Email: gugale.harsh@gmail.com

Github & IRC Nickname: harshgugale

GSoC Proposal: click here