GSoC 2018 Blog
Bit Error Ratio Analyzer using Litex

1) Started debugging the simulation files. 2) tx init sequence is working fine. DRP read is not working in simulation, so rx init is not getting completed. 4) Tried bypassing the init sequence but rx ready still does not get asserted. 5) Also, integrated PRBS modules prepared by me with the simulation file. Next Steps: 1) Continue step by step debugging of simulation file. Figure out problem with DRP read.

Completed the GUI design and event handling class for controlling PRBS module on the Arty Board. Code: 1) The code may be found here: https://github.com/harshgugale/ber_analyzer_arty. ber_gui.py is the event handling class and calls the designed GUI. 2) Requires local install of LiteX libraries and execution of litex_server.py 3) GTP2 event handlers have not been added. I will introduce more parameters in the GUI after successful testing of the high-speed serial interface. Features: 1) Complete, real-time control of PRBS settings, 8b10b encoding, percentage error injection using GUI. 2) Dynamic updating of BER after every 1 second. Next Steps: 1) I will now start an in-depth analysis of the GTP simulation.  

1) Understood code here: https://github.com/enjoy-digital/transceiver_test/blob/master/sim/gtp_7series_sim.py and simulated the same. The simulation does not work the way it should. Tried debugging it, but will require some more time. 2) Tried to bypass the init sequence and integrated PRBS modules prepared by me with GTP transceiver simulation file. This too does not work correctly. I will need to look at GTP primitive (both COMMON and CHANNEL) parameters individually and try to figure out the problem. 2) Meanwhile, I have also started working on the BER Analyzer GUI. A rudimentary one may be found here: https://github.com/harshgugale/ber_analyzer_arty/blob/master/ber_gui.py Next steps : 1) Limited event handling has been added to GUI till now. I will add remaining handlers. 2) Step by step debug of GTP simulation file. For now, The PRBS module generates the correct output so I will start by debugging the TX transmission interface. I'll verify that gtp_txp and gtp_txn gi

1) I was out of station for three days, so could not work. I have resumed work from today. 2) We have decided to first simulate a loopback test using 7 series transceiver wizard. 3) I have started reading these files: - https://github.com/enjoy-digital/transceiver_test/blob/master/sim/gtp_7series_sim.py - https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf - https://www.xilinx.com/support/documentation/user_guides/ug482_7Series_GTP_Transceivers.pdf 4) I will then integrate my PRBS Module with the gtp_7series_sim.py.

8b10b encoding functionality has been successfully integrated and tested on the Arty Board. Code: 1) All files may be found here : https://github.com/harshgugale/ber_analyzer_arty 2) Local install of LiteX files is necessary. 3) Control from host may be done using this control abstraction file : https://github.com/harshgugale/ber_analyzer_arty/blob/master/control_prbs.py Features: 1) PRBS RX now has autosynchronization feature, which takes care of the initial latency. 2) Host selectable enabling and disabling of 8b10b encoding/decoding. 3) Host selectable percentage error injection. Next Steps: 1) FPGA with high speed serial transceivers should be with me in a few days. I will spend some time reading the data sheet and implementing few basic designs. 2) Customize Xilinx 7-series transceiver logiCore for some simple loopback test using inbuilt PRBS generators and Checkers.

1) Read about Clock Domain Crossing including designs to mitigate data loss, metastability, and incoherency. Read about various FIFO and buffer architectures for CDC. 2) Completed integrating the 8b10b module with PRBS module. Stuck with some latency and synchronizing issue. Next Steps : 1) My mentor, Florent, has sent an FPGA with high-frequency serial transceivers which should reach me in a couple of days. I will spend some time reading its datasheet and trying to implementing some basic designs. 2) Solve this latency related issue by working with Florent.

1) Understood code here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/code_8b10b.py 2) Committed some changes to prbs control abstraction class here: https://github.com/harshgugale/ber_analyzer_arty/blob/master/test_host/control_prbs.py Next steps : 1) Add 8b/10b encoding and decoding functionality over PRBS Tx and Rx respectively. Decide on various serial line rates which can support this encoding while ensuring minimum latency.

I completed the design and testing of the PRBS transmitter and receiver module on the Arty Board. Code : 1) All modules may be found here https://github.com/harshgugale/ber_analyzer_arty. 2) Requires local install of LiteX libraries. 3) Calculation of BER may be done using the files here: https://github.com/harshgugale/ber_analyzer_arty/tree/master/test_host . File control_prbs.py is an abstraction file for BER calculation. Features : 1) Host selectable config for PRBS 7, 15, 23 and 31. 2) Implemented a lookahead PRBS generator for supporting multi - Gbps serial linerates for GTP transceivers (which will be implemented later). 3) Host selectable percentage error injection. Next steps : 1) Add 8b/10b encoding and decoding functionality.

1) Added global bit error calculation functionality via a 4 stage pipeline (From Tx PRBS bit pattern generation to the calculation of total bit error in transreception). 2) Added functionality to generate controlled bit error in the transmitted bits. 3) Created base.py script to integrate this PRBS transreception module with LiteX libraries. This enables me to change PRBS pattern settings, change controlled error settings and inform host about the global bit error. 4) Simulated the design to verify that they indeed work as desired. 5) All the coded modules may be found here https://github.com/harshgugale/ber_analyzer_arty. Next steps : 1) Implement the design on Arty board and debug if there are any issues