GSoC 2018 Blog
Bit Error Ratio Analyzer using Litex

Project Overview: Bit Error Ratio testers are used to test the quality of signal transreception on a given medium. They also assist in tuning transmitter and receiver parameters so that medium fidelity is maximized. Several secure IP cores exist which may be implemented on FPGA to serve this purpose, one example being iBERT LogiCore by Xilinx. iBERT LogiCore is a GUI application which provides a nice interface for the user to change parameters such as prbs config, output swing, pre/post cursor settings, equalizer settings, etc. and observe the changes in bit error ratio. My project, as part of Google Summer of Code 2018, was to design and test an opensource equivalent of iBERT LogiCore and add most features as detailed in its datasheet. All files are coded in python-based HDL framework - migen and use an SOC ecosystem based on Migen - LiteX , to create the necessary host connections. This IP majorly uses 7 series MGT transceiver primitives GTPE2_COMMON and GTPE2_CHANNEL. Code

I have completed coding a basic version of Bit Error Ratio Analyser. Features: 1) MGT Settings: 2) BER Settings: 3) DRP Interface Code :  1) All coded files may be found here: https://github.com/harshgugale/ber_analyzer_gtp  2) Litex local install is necessary. Next Steps: 1) Thorough testing of these modules is left. I will begin thorough testing from Monday when Florent will be back to his office. 2) I will also try to complete documenting my code until then. My next post will contain the final report for this GSoC project. It will contain information to reproduce results, list coded features and possible improvements. 3) I had planned to also plot a statistical eye, but I feel that due to time constraints this wont be possible. I will work on this after GSoC.

1) Completed integrating functionality to read/write from the host through DRP. 2) BER Analyzer now supports TX/RX reset from host, PLL lock status intimation, changing loopback mode (Near End PMA or Normal), changing TX/RX polarity inversion. 3) Read about eye scan architecture. Next Steps: 1) Using DRP write, include functionality to change pre emph, post emph and output swing in the next two days. 2) Update GUI with handlers to support these functions 3) I will start coding and plotting the eye scan from next week.

1) Completed integrating TX/RX host reset functionality. 2) Also integrated PLL Status intimation to user. 3) Coded DRP read/write interface to work with the host commands and the RX init commands. Next Steps : 1) Test DRP read/write on the FPGA. 2) Start by adding feature: 1) Loopback mode 2) TX/RX Polarity

1) Completed integration of clock Aligner class and testing of Near end PMA loopback on te014 board. 2) All PRBS features tested on Arty board now work on te014 board over MGTs. GUI has not been updated with event handlers specific to MGT settings. Code: 1) Coded files may be found here : https://github.com/harshgugale/ber_analyzer_gtp Next Steps: 1) I have started with the addition of TX/RX reset from the host. I will complete the same in the next two days. 2) I can then integrate DRP read/write class with the main class and add precursor, post-cursor and output swing control.

1) Implemented simple PMA loopback on te014 board with PRBS data. This was achieved without alignment. 2) There seems to be some issue with the BruteForceClockAligner class and hence the receiver never completes reseting to output the correct phase. 3) Updated the GUI to include MGT functions. Next steps: 1) Look into the issue with the clock aligner class. 2) Add MGT setting event handlers.

1) Integrated GTP Primitives, clock aligner file, top class to connect GTP COMMON and CHANNEL with base SOC file prepared using LiteX libraries 2) Coded DRP FSM class to read/write through DRP interface. 3) Updated GUI to inform the user regarding - PLL lock status, MGT Link, TX/RX Polarity, TX/RX reset. Next Steps: 1) Due to some connectivity issues, I could not implement my design on the FPGA. I will resolve the same and implement in the next 3 days.