21st - 24th July
1) Completed integrating TX/RX host reset functionality.
2) Also integrated PLL Status intimation to user.
3) Coded DRP read/write interface to work with the host commands and the RX init commands.
Next Steps :
1) Test DRP read/write on the FPGA.
2) Start by adding feature: 1) Loopback mode 2) TX/RX Polarity
2) Also integrated PLL Status intimation to user.
3) Coded DRP read/write interface to work with the host commands and the RX init commands.
Next Steps :
1) Test DRP read/write on the FPGA.
2) Start by adding feature: 1) Loopback mode 2) TX/RX Polarity
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