13th - 16th July

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1) Integrated GTP Primitives, clock aligner file, top class to connect GTP COMMON and CHANNEL with base SOC file prepared using LiteX libraries

2) Coded DRP FSM class to read/write through DRP interface.

3) Updated GUI to inform the user regarding - PLL lock status, MGT Link, TX/RX Polarity, TX/RX reset.

Next Steps:
1) Due to some connectivity issues, I could not implement my design on the FPGA. I will resolve the same and implement in the next 3 days.

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