27th - 30th June

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1) Started debugging the simulation files.

2) tx init sequence is working fine. DRP read is not working in simulation, so rx init is not getting completed.

4) Tried bypassing the init sequence but rx ready still does not get asserted.

5) Also, integrated PRBS modules prepared by me with the simulation file.

Next Steps:
1) Continue step by step debugging of simulation file. Figure out problem with DRP read.

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