25th - 27th May

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1) Analysed working of some more Migen modules such as migen.fhdl.structure.py and migen.genlib.cdc.py to become familiar with how Migen handles datatypes.

2) Since clock domain crossing will be a significant part of the project, I analyzed how Migen takes care of synchronizations and avoids metastability. Saw the working of Multireg, Clockdomainrenamer functions.

3) Understood how PRBS module (https://github.com/enjoy-digital/transceiver_test/blob/master/transceiver/prbs.py) is coded and how to use it.

4) Read some literature about 8b/10b encoding. Understood the code here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/code_8b10b.py

5) Started coding the Tx_top module (architecture and placement of the same can be found in the previous post). Can't seem to figure out the generation of invalid data for the first 2 clock cycles from this modules. We have decided to go forward with this since the PRBS checker module should be able to synchronize the same at the RX.

Next Steps :

1) In the next 3 days, I code PRBS transmitter and receiver module and introduce functionality to calculate the total bit error.

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