22nd - 24th May
1) I now have a complete block level understanding of the GTP transceivers.
This is the user guide referred: https://www.xilinx.com/support/documentation/user_guides/ug482_7Series_GTP_Transceivers.pdf
Next Steps :
1) As discussed with Florent, I will first implement the complete system on my Arty Board which will validate the datapath.
2) Roughly, following modules will be coded, integrated and verified on FPGA.
3) The left half of the system will be created using LiteX libraries.
4) Work for the next three days would be to code and integrate the modules and if time permits implement the design and perform a loopback test.
This is the user guide referred: https://www.xilinx.com/support/documentation/user_guides/ug482_7Series_GTP_Transceivers.pdf
Next Steps :
1) As discussed with Florent, I will first implement the complete system on my Arty Board which will validate the datapath.
2) Roughly, following modules will be coded, integrated and verified on FPGA.
3) The left half of the system will be created using LiteX libraries.
4) Work for the next three days would be to code and integrate the modules and if time permits implement the design and perform a loopback test.
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