31st May - 2nd June

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1) Added global bit error calculation functionality via a 4 stage pipeline (From Tx PRBS bit pattern generation to the calculation of total bit error in transreception).

2) Added functionality to generate controlled bit error in the transmitted bits.

3) Created base.py script to integrate this PRBS transreception module with LiteX libraries. This enables me to change PRBS pattern settings, change controlled error settings and inform host about the global bit error.

4) Simulated the design to verify that they indeed work as desired.

5) All the coded modules may be found here https://github.com/harshgugale/ber_analyzer_arty.

Next steps :

1) Implement the design on Arty board and debug if there are any issues

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