9th - 12th June

-
1) Read about Clock Domain Crossing including designs to mitigate data loss, metastability, and incoherency. Read about various FIFO and buffer architectures for CDC.

2) Completed integrating the 8b10b module with PRBS module. Stuck with some latency and synchronizing issue.

Next Steps :
1) My mentor, Florent, has sent an FPGA with high-frequency serial transceivers which should reach me in a couple of days. I will spend some time reading its datasheet and trying to implementing some basic designs.

2) Solve this latency related issue by working with Florent.

Comments

Post a Comment

Popular posts from this blog

GSoC 2018 Final Report

-
Image
Project Overview: Bit Error Ratio testers are used to test the quality of signal transreception on a given medium. They also assist in tuning transmitter and receiver parameters so that medium fidelity is maximized. Several secure IP cores exist which may be implemented on FPGA to serve this purpose, one example being iBERT LogiCore by Xilinx. iBERT LogiCore is a GUI application which provides a nice interface for the user to change parameters such as prbs config, output swing, pre/post cursor settings, equalizer settings, etc. and observe the changes in bit error ratio. My project, as part of Google Summer of Code 2018, was to design and test an opensource equivalent of iBERT LogiCore and add most features as detailed in its datasheet. All files are coded in python-based HDL framework - migen and use an SOC ecosystem based on Migen - LiteX , to create the necessary host connections. This IP majorly uses 7 series MGT transceiver primitives GTPE2_COMMON and GTPE2_CHANNEL. Code
Read more

17th - 19th July

-
Image
1) Implemented simple PMA loopback on te014 board with PRBS data. This was achieved without alignment. 2) There seems to be some issue with the BruteForceClockAligner class and hence the receiver never completes reseting to output the correct phase. 3) Updated the GUI to include MGT functions. Next steps: 1) Look into the issue with the clock aligner class. 2) Add MGT setting event handlers.
Read more

Introduction

-
Hi there! Welcome to my blog. About me :  I am Harsh Gugale, a senior UG student at Indian Institute of Technology (BHU) Varanasi, pursuing a bachelors degree in Electronics Engg. About Google Summer of Code :  Google Summer of Code (GSoC) is a summer internship program by Google where students can work with open source organizations from around the world, contribute to these organizations by either working on existing projects or something entirely new and in turn get paid from Google in doing so! (Cool isn't it?) Organization : I am taking part in GSoC 2018 under TimVideos . TimVideos.us is a group of exciting projects which provide both hardware and software solutions to record and live video stream conferences, meetings, and other presentations. Project : Bit error ratio testers are used to test the quality of signal trans-reception. They are routinely used to test boards with high-speed serial links and tune parameters so that the medium fidelity is maximized. In
Read more