Progress Report

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Updates till now :

1) Simulation and testing (on Arty Board) of the PRBS trans reception module are complete. All features concerning BERT settings for a single MGT available in IBERT logiCore have been integrated. Additionally, user selectable 8b10b encoding module has been incorporated.

2) GUI to control PRBS config, inject user selectable error, display Bit Error Ratio, and Link availability has been designed and tested on Arty Board.


3) Completed the simulation of a simple near-end PMA loopback of Multi-Gigabit serial trans-reception module. Also, integrated PRBS modules prepared earlier with this file.

4) Unfortunately, the FPGA sent by my mentor, Florent is stuck at the customs office in India. I will order a new board for myself, but it may take some time to arrive.

Code :

1) All python files may be found here: https://github.com/harshgugale.
ber_analyser_gtp has files to simulate a loopback test using Xilinx Vivado. ber_analyser_arty contains GUI files and associated PRBS module.

2) LiteX local install is necessary.

Next steps :

1) Start adding features by adding some simple functions to the GUI, specific to serial trans reception such as PLL lock status, TX/RX reset, etc.


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